DRAMS having folded lines are well known, and typically are formed of rows or word lines and columns or bit lines, the columns each being formed of a complementary pair of the bit lines. Storage capacitors are located at the intersection of each word line and bit line, which store charge indicative of zeroes and ones. For example, the presence of a charge on a capacitor can signify the existence of a logic one. The capacitors are connected to the bit lines through access transistors, which are enabled from the word lines. Each complementary pair of bit lines is in turn connected through transistors to corresponding data bus lines.
In order to speed up reading and writing of the memory, the bit lines are pre-charged to a voltage V.sub.BLP which is half of the supply voltage V.sub.DD and the reference plate of the storage capacitor is charged to a voltage V.sub.CP which is half of the supply voltage V.sub.DD. Pre-charging the bit lines to half the supply voltage reduces signal swing on the bit lines, which reduces peak current and allows faster reading.
Various circuits have been implemented to generate the storage capacitor reference voltage V.sub.CP and the bit line pre-charge voltage V.sub.BLP. A low impedance drive is required for V.sub.BLP to maintain the bit line pre-charge level, while a high impedance drive is required for V.sub.CP to prevent voltage supply noise from charging the storage capacitor reference level and inadvertently enabling the access transistor and causing a corrupt read operation. A typical circuit is described in U.S. Pat. No. 5,255,232 to Foss et. al. and incorporated herein by reference.
Recently, the DRAM market has increased demands for memories with higher storage capacity and low power consumption. Higher storage capacity requires a larger number of storage capacitors which in turn requires an associated increase in the current supply drive capabilities of the cell plate and bit line precharge voltage generators. This may be achieved by increasing the size of the drive transistors supplying V.sub.CP and V.sub.BLP in order to supply sufficient current to compensate for the increased load on V.sub.BLP or the gate biases of the drive transistors could be adjusted in order to increase their current supply capability. A disadvantage of both techniques is the resulting increased standby current, while a disadvantage of the second technique is that it cannot be applied to a single transistor.
Furthermore, any of these changes should be capable of being implemented without an increased set-up time during power-up. It would also be advantageous to stabilize V.sub.BLP and V.sub.CP level during the access transistor on state and to minimize the stand by current for the V.sub.BLP and V.sub.CP circuit.